1. Field of the Invention
The present invention relates to an audio signal data processing system.
2. Description of Background Information
There are known audio signal data processing systems capable of controlling the sound field by which concert-hall (or theater) acoustics with reverberation sounds and presence, for example, are created in a listening room or in an automobile. An example of such a audio data processing system is disclosed in Japanese Patent Application Laid Open No. 64-72615. In such audio signal processing systems, a DSP (digital signal processor) is provided for controlling the sound field by digitally processing an audio signal output from an audio signal source such as a tuner.
The DSP is generally equipped with an arithmetic unit for executing operations such as the operations of the four rules of arithmetic, a data memory for storing the audio signal data to be supplied to the arithmetic unit, and a coefficient memory for storing coefficient data to be multiplied by the signal data stored in the data memory. Moreover, the DSP is configured so that an external memory for delaying the signal data can be connected from outside the system. Furthermore, the DSP is equipped with a delay time memory for storing delay time data indicating the time interval between the writing and reading of the signal data into and from the delay memory. In the DSP, the structure is such that the signal data is transferred between memories and also from a memory to the arithmetic unit in accordance with predetermined programs, in order that a calculating process for the signal data can be repeatedly executed at high speed. For example, an acoustic field is created by generating data from reflected sounds in consideration of the level attenuation in the following manner. At first the incoming signal data is transferred to the delay memory to delay the signal data so that delayed signal data is produced. Then the delayed signal data is transferred, via the data memory, to the arithmetic unit where the delayed signal data is multiplied by the coefficient data.
The coefficient data and the delay time data are rewritten by new data every time the sound field mode is changed by a manual operation, such new data being supplied from a microcomputer provided external to the DSP. With DSP the constructed in this way, a variety of acoustic fields can be created.
However, there has been a problem as follows. Since the frequency spectrum of the actual reflective sound changes depend on the wall material, so that an acoustic field which is equivalent to the actual sound field cannot always be obtained.
On the other hand, the program to be executed in the DSP is written in a rewritable memory such as the RAM in the DSP, and changed by the microcomputer external to the DSP every time the sound field mode is switched over by manual operation. By changing the program, various sound fields can be created.
In conventional DSPs, a circuit for controlling writing and reading addresses is constructed as shown in FIG. 7. This control circuit is used for controlling a delay memory for delaying 24-bit signal data, which is constituted by two dynamic RAMs each having 64K.times.4 bits. In this control circuit, a delay time data RAM 161 stores delay time data. The delay time data is provided for each access (reading/writing) of signal data, and the difference between delay time data for reading and delay time data for writing represents the delay time. A register 162 is connected to the delay time data RAM 161, and the delay time data read-out from the RAM 161 is held therein. The control circuit includes a rewritable register 163 holding ring length data i.e. data representing the maximum delay time. The delay time data and the ring length data are 14-bit data. The data from the registers 162 and 163 are supplied to a subtractor 164 where a modulo subtraction between the ring length data and the delay time data is performed. The result of the subtraction is used as base address data during the access to the delay RAM.
The modulo subtraction is performed as follows. If the delay time data is equal to zero, base address data is determined to be equal to the ring length data. If, on the other hand, the delay time data is not equal to zero, the base address data is determined to be equal to a value obtained by decreasing the delay time data by 1.
The result of modulo subtraction is transferred to the delay time data RAM 161, to be used as the delay time data in the next sampling period. In other words, the delay time data is varied by ring counting within the ring length data while being decremented at each sampling interval.
In delay memory access circuit 165 to which data of the subtractor 164 is output, access to the delay memory is performed by a so-called "page mode". For explanatory purposes, the high-order six bits of the output data from the subtractor 164 are denoted by [BAH], and the low-order eight bits of the output data of the subtractor 164 are denoted by [BAL]. The delay memory access circuit 165 is configured to add two bits "00" to [BAH], thereby producing 00[BAH] which is to be used as the base address data. As shown in FIG. 8, the [BAL]is supplied as a row address to the address terminal of the delay memory in synchronism with the falling edge of a RAS (Row Address Strobe) signal in the delay memory access circuit 165. Similarly, the 00[BAH] is supplied as a column address to the address terminal of the delay memory at the time of the first falling edge of a CAS (Column Address Strobe) signal within one sampling period. Furthermore 01 [BAH] is supplied at the time of the second falling edge of the CAS signal, and 10[BAH] is supplied at the time of the third falling edge of the CAS signal. In short, two high-order bits of the column address are up-counted.
In the manner described above, the 24-bit signal data is delayed in the delay memory which is comprised of two dynamic RAMs each having 64K.times.4 bits.
However, in the conventional DSP described above, the number of times of access is three, and the two high-order bits of the column address will not become "11". This means that one fourth of the total capacity of the delay memory is not used at all. Because of this reason there is the problem that the maximum delay time is limited to be less than the ultimate value.
The dynamic RAM of 64K.times.4 bits has a refresh cycle of 4 milliseconds. If all of 256 row addresses are not accessed in this time period, the correctness of stored contents can not be assured. Since the number of row address during the access of 24-bit signal data is "1", the number of row addresses which can be accessed at a rate of one reading/writing time per 4 milliseconds becomes equal to 128 (4 milliseconds.div.(1/32 KHz)) when the conventional DSP is operated at a sampling frequency of 32 KHz. Thus, there is the problem that only half of the 256 row addresses are accessed under the above-condition.
Practically, there are several reading/writing cycles in each sampling period, and the memory can be refreshed if a certain condition is assigned to the delay time data. However, this solution imposes some limitation in the delay time which can be obtained. Therefore, the conventional DSP suffers a deficiency in handling data.
Furthermore, the audio data signal processing system generally is provided with an A/D converter for converting the incoming analog audio signal to digital audio signal data to be supplied to the DSP. However, there is the problem that off-set adjustment of the A/D converter must be performed thoroughly so that the output data of the A/D converter becomes conversion data for the incoming audio data with respect to a reference value.